1. Field of the Invention
The invention relates to a solid-state imaging device used for various image sensors, particularly, relates to a solid-state imaging device and an imaging apparatus capable of securing efficient operation with respect to load changes at the time of activation and other occasions.
2. Description of the Related Art
In related arts, a MOS-type solid-state imaging device is known as this kind of solid-state imaging device. In the MOS-type solid-state imaging devices, a solid-state imaging device having a system in which signal charge of a photodiode (photoelectric converter) included in a pixel is read out after the charge is transferred to a detection region using a transfer transistor is known.
The MOS-type solid-state imaging device having this system is different from a CCD-type solid-state imaging device, in which a CMOS logic circuit is mounted on the same chip, and pixels are operated by one power source of low voltage which is the same as the logic circuit. Therefore, for example, when the transfer transistor is an n-channel MOS transistor, gate voltage of the transfer transistor in the pixel had two values of 0V and a power supply voltage Vdd. In related arts, negative voltage is applied to the gate of the transfer transistor in order to prevent dark current, thereby achieving improvement of image quality (for example, refer to JP-A-2002-217397 (Patent Document 1)).
FIG. 10 is a circuit diagram showing an example of a MOS-type solid-state imaging device in the related art.
A MOS-solid-state imaging device 1 includes a sensor unit 3 in which plural pixels 2 are arranged in a matrix manner, a vertical scanning circuit 4 and a horizontal scanning circuit 5 driving the sensor unit 3, and signal holding circuits 6 receiving signals of pixels 2 of one row in the sensor unit 3. In FIG. 10, the pixels 2 are drawn as 2×2 pixels for convenience, however, many pixels are actually arranged.
Each pixel 2 includes a photodiode PD performing photoelectric conversion, a transfer transistor QT transferring signal charge of the photodiode PD to a detection region (floating diffusion) FD, an amplifying transistor QA outputting potential at the detection region FD to a vertical signal line 8, an address transistor QD selecting a row of the pixel 2 and a reset transistor QR resetting potential of the detection region FD.
In the pixel 2, a gate of the address transistor QD is connected to a vertical selection line 10 from the vertical scanning circuit 4. A gate of the reset transistor QR is connected to a reset line 11, and a gate of the transfer transistor QT is connected to a vertical readout line 9. A load transistor QL having a function of a constant current source is connected to one end of the vertical signal line 8 and the signal holding circuit 6 is connected to the other end thereof. An output signal of each pixel is taken by the signal holding circuit 6 through the vertical signal line 8 and outputted to a circuit of a sequential stage through an OR gate 15 by driving the horizontal scanning circuit 5.
The vertical scanning circuit 4 is provided with three buffer circuits 12, 13 and 14 at each pixel row. The buffer circuits 12 and 13 output the power supply voltage Vdd to the vertical selection line 10 or the reset line 11 at the output side when a low-level pulse is inputted from the side of the vertical scanning circuit 4 and output ground voltage to the vertical selection line 10 or the reset line 11 at the output side when a high-level pulse is inputted.
In this example, a negative voltage generating circuit 7 (for example, a charge pump circuit) is provided as a means for applying negative voltage to the gate of the transfer transistor QT during a charge storage period. The output of the negative voltage generating circuit 7 is inputted to the buffer circuit 14 connected to the vertical readout line 9.
The buffer circuit 14 outputs the power supply voltage Vdd to the vertical readout line 9 at the output side when a low-level pulse is inputted from the side of the vertical scanning circuit 4 and outputs negative voltage to the vertical readout line 9 at the outside side when a high-level pulse is inputted.
Next, shutter operation in the above MOS-type solid-state imaging device 1 is shown in FIG. 11A and FIG. 11B. The operation is divided into a charge storage period and a readout period. All pixels in the same row are processed at the same timing. There are a normal shutter mode (FIG. 11A) in which storage and readout are performed by each row with continuous operation and the charge is outputted for the number of rows, and a global shutter mode (FIG. 11B) in which, after charge storage of all pixels are performed, readout is performed at each row. In FIG. 11A and FIG. 11B, a reset gate signal is denoted as φR, and a transfer gate signal is denoted as φT.
In the normal shutter mode (FIG. 11A), first, the photodiode PD and the detection region FD are reset, then, charge storage is started. During the readout period after charge storage is finished, signal charge stored in the photodiode PD is transferred to the detection region FD, signal voltage corresponding to the FD is transmitted to the signal holding circuit 6 by a source follower including the amplifying transistor QA and the load transistor QL. In the global shutter mode, reset is performed by turning on a global shutter signal, and charge storage of all pixels is performed at the same time by turning off the global shutter signal, then, charge storage of all pixels is finished at the same time by a mechanical shutter. The readout period after that is the same as the control sequence of the normal shutter for one row, and this sequence is repeated for the number of rows to output signals of all pixels.
Next, a boosting charge pump circuit in the related art is shown in FIG. 12 (for example, refer to JP-A-6-351229 (Patent Document 2)).
As shown in the drawing, the charge pump circuit includes an oscillation circuit 201, an amplifier 202, a reference voltage source 203, switches SW1 to SW4, voltage-dividing resistances R1, R2, a pump capacitor (pump capacitance) Cp, an output capacitor COUT, an inverter 204 and the like. A power supply voltage Va by the amplifier 202 is applied to both ends of the pump capacitor Cp through the switches SW1, SW4, and one end of the pump capacitor Cp is connected to the output capacitor COUT through the switch SW2 and the other end is grounded through the switch SW3.
Then, charge from the amplifier 202 is charged in the pump capacitor Cp by the oscillation circuit 201, the inverter 204 and switching operation by the switches SW1 to SW4, and the boosted output is smoothed at the output capacitor COUT to be outputted as an output voltage VOUT.
In this circuit, the output voltage VOUT is divided by the resistances R1, R2, and the divided voltage and a reference voltage VREF1 are compared by the amplifier 202, and output voltage Va of the amplifier 202 is used as the power supply for the charge pump circuit to perform boosting operation.
Though the configuration shown in FIG. 12 is a circuit configuration of the boosting charge pump, a feedback system using an inverting charge pump amplifier can also be realized by the similar configuration. The inverting charge pump circuit is shown in FIG. 13. The same signs are put to components common to the FIG. 12.
As shown in the drawing, in this circuit, one end of the pump capacitor Cp is grounded through the switch SW1, and the other end is connected to the drive voltage Vdd through the switch SW3.
Then, new voltage values are set to respective reference voltages, and at first, charge is stored in the pump capacitor Cp by connecting between the Vdd and GND with the switches SW 1 and SW 3 as a sequence of switching. After that, the switch SW4 is connected to the output voltage Va of the amplifier 202 and the reverse end is connected to the switch SW2 to generate negative voltage output VOUT.